The present invention relates generally to delay lock circuits and in particular the present invention relates to integrated circuits with a non-volatile delay register.
As the level of integration of digital integrated circuits increases, the generation and distribution of internal clock signals becomes more problematic. For example, distributing synchronous clock signals to many registers (ed.g. thousands) throughout a very large scale integrated circuit can introduce significant clock skewing due to the parasitic resistive and capacitive loading of the clock signal lines.
One technique for minimizing clock skewing due to mass distribution of a synchronous clock signal is to use a phase lock loop (PLL) whereby a reference clock signal is distributed and used to generate and synchronize many local clock signals. The PLL can also be used to multiply the frequency of the reference clock signal thereby generating local clock signals which are synchronous frequency multiples of the reference clock signal.
Implementing a PLL in a typical digital integrated circuit is undesirable since the typical PLL requires the use of analog circuits, such as a voltage controlled oscillator, phase detector, charge pump, and low pass filter.
Other types of locking loops have been commonly used for generating timing reference signals used in electronic circuits. One example of such a locking loop is a delay lock loop or digital delay lock loop. The operation of exemplary locking circuitry or delay lock loops is described in the following patents, the disclosures of which are incorporated by reference: U.S. Pat. Nos. 6,150,856, 5,663,665, 5,771,264, 5,642,082, and 5,744,991. Each of these delay lock circuitry architectures requires an iterative synchronization, or lock, operation. This lock operation is typically performed during a power-up operation and must be performed prior to operating the integrated circuit incorporating the delay lock circuit.
For reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a delay lock circuit with a reduced synchronize time.
The above-mentioned problems with delay lock circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, an integrated circuit comprises a clock connection to receive an external clock signal, a delay circuit coupled to the clock connection to provide a delay output clock signal on an output connection, and a phase detector coupled to the clock connection and the output connection of the delay circuit. The phase detector determines a timing difference between the external clock signal and the delay output clock signal. A delay register is coupled to the delay circuit. A data content of the delay register adjusts a delay time of the delay circuit, and a non-volatile register is coupled to load the delay register with initial start data.
In another embodiment, a synchronous memory device comprises a clock connection to receive an external clock signal, a delay circuit coupled to the clock connection to provide a delay output clock signal on an output connection, and a delay register coupled to the delay circuit. A data content of the delay register adjusts a delay time of the delay circuit. A non-volatile register is coupled to load the delay register with initial start data.
A method of operating a delay circuit comprises initiating a clock synchronization operation to synchronize an output signal of the delay circuit with a clock signal, loading a volatile register with initial start data stored in a non-volatile register, and adjusting the volatile register to control a delay time of the delay circuit.
A method of operating a memory device comprises synchronizing an internal clock signal with an external clock signal using a delay lock circuit. The delay lock circuit comprises a delay register. A contents of the delay register is copied to a non-volatile register after the internal clock signal is synchronized with the external clock signal.